1. Field of the Invention
The present invention relates to a clock generator, and more particularly, to a spread spectrum clock generator.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional Phase Lock Loop (PLL) 100. As shown in FIG. 1, the PLL 100 comprises a Phase/Frequency Detector (PFD) 110, a charge pump 120, two capacitors C1 and C2, a resistor R1, and a Voltage Control Oscillator (VCO) 130. The PLL 100 receives a clock signal S1 and accordingly generates a clock signal S2. The phase and frequency of the signal S2 is the same as those of the signal S1. The PFD 110 comprises two input ends and an output end. One input end of the PFD 110 receives the clock signal S1 and the other input end of the PFD 110 receives the signal S2 fed back from the output end of the PFD 110. The PFD 110 transmits the control signals X1 or X2 to the charge pump 120 according to the phase difference and the frequency difference between the signals S1 and S2. When the frequency/phase of the signal S2 is higher than that of the signal S1, the PFD 110 transmits the control signal X1. When the frequency/phase of the signal S2 is lower than that of the signal S1, the PFD 110 transmits the control signal X2. When the frequency/phase of the signal S2 is the same as that of the signal S1, the PFD 110 does not transmit the control signals X1 or X2. The input end of the charge pump 120 is coupled to the output end of the PFD 110 for receiving the control signals X1 or X2 and accordingly sourcing or sinking a current Ip with a constant value. That is, when receiving the control signal X1, the charge pump 120 sources the current Ip. When receiving the control signal X2, the charge pump 120 sinks the current Ip. When not receiving the control signals X1 or X2, the charge pump 120 does not source or sink the current Ip. The capacitor C2 is coupled between the output end of the charge pump 120 (node A) and a ground end. One end of the resistor R1 is coupled to the node A, and the other end of the resistor R1 is coupled to the capacitor C1. The capacitor C1 is coupled between the resistor R1 and the ground end. Thus, the voltage VA on the node A rises or falls as the charge pump 120 sources or sinks the current Ip. When the charge pump 120 keeps sourcing the current Ip, the voltage VA keeps rising as well. When the charge pump 120 keeps sinking the current Ip, the voltage VA keeps falling as well. The input end of the VCO 130 is coupled to the node A. The VCO 130 outputs the clock signal S2 having the frequency according to the voltage VA on the node A. When the voltage VA rises, the frequency of the signal S2 rises as well. When the voltage VA falls, the frequency of the signal S2 falls as well. The clock signal S2 is also fed back to the PFD 110. In this way, the conventional PLL 100 outputs an clock signal with the same frequency and the same phase as the input clock signal.
However, any electronic devices with high frequencies generate noises. The noises interfere with other electronic device through the power lines or air. Many countries have restriction on the degree the electronic device interference such as EN55015, FCC PART 18, and JIS. And because the conventional PLL 100 generates the clock signal S2 with concentrated power so that the power of the clock signal S2 possibly exceeds the restriction, causing interference with other electronic devices.